This invention relates to the general field of microelectronics, and in particular to the technology of bonding substrate materials to semiconductor wafers containing circuitry.
The attachment of monolithic integrated circuits to electrical headers is an important and difficult process. The substrate material forming the header provides mechanical support for the fragile wafer, as well as a thermal path for removing heat generated by the circuits formed on the wafer. Recently, wafer scale integration has been used for interconnecting numerous circuits on an single wafer, thereby making use of an entire wafer for one application; for example, U.S. Pat. No. 4,823,136 to Nathanson et al. entitled "Transmit-Receive Means for Phased-Array Active Antenna System Using RF Redundancy." Wafer scale integration compounds the mounting and thermal stress problems, and can require numerous interconnections between various portions of the wafer, and between the wafer and circuitry separate from the wafer for power and signal takeoffs.
The attachment process for gallium arsenide wafers has traditionally been accomplished by providing a thick gold metalization to the inactive side of the wafer, as well as to the top of the substrate material. The two metallized surfaces are then joined with a solder whose composition is essentially 80 wt. % gold and 20 wt. % tin. In addition to the obvious cost of working with thick layers of gold, this process often yields poor results due to the high temperature and resulting high stress levels induced into the gallium arsenide wafer. The melting temperature of 80/20 gold/tin solder is approximately 280.degree. C. The temperature required for good solder flow is even higher because as the solder combines with the gold metalization on the gallium arsenide wafer and the substrate, the liquids temperature increases. Differential expansion of the gallium arsenide wafer and the substrate material can severely stress the wafer, resulting either in immediate cracking of the wafer or in reduced long term stability of the circuit or device. The use of solder having a composition of 10 wt. % gold and 90 wt. % tin allows the use of a lower melting temperature (approximately 217.degree. C.), however, such a solder rapidly forms higher melting point intermetallic compounds, such as AuSn.sub.4 which are not suitable for soldering. Another problem with the standard soldering technique is that excess solder can be squeezed laterally across the surface of the wafer to areas where it is not intended to make contact, causing failures of the circuit through electrical shorts. Furthermore, the voids which are inevitably generated a the molten solder solidifies and shrinks in volume can coalesce, leaving large void areas which constitute regions of low thermal conductivity and inhomogeneous stress distribution.
Similar bonding problems have been encountered in the field of silicon wafer devices. For silicon devices, improved processes have been developed by using various combinations of materials for both the metalization layers and the solder material. For example, Finn et al., in PCT International Publication Number WO 82/02457, disclose a two layer metalization of the silicon wafer, using first chromium then gold or an alternative material. The wafer is then soldered to the metal, or metallized, substrate using a tin preform, heated in an inert atmosphere. Ivett et al., in U.S. Pat. No. 4,023,725, disclose the use of a two layer metalization of the silicon wafer, using first silver or titanium then a thin layer of rhodium or an alternative material. The wafer is then soldered to the substrate with a lead based solder. These processes, developed specifically for silicon based devices, require soldering temperatures of 275.degree.-315.degree. C.
Progress in the technology for bonding gallium arsenide wafers to substrate materials has been limited. Altemus et al, in U.S. Pat. No. 3,986,251, disclose a process for bonding gallium-type devices to a metallized substrate. The gallium wafer undergoes a surface preparation process, then it is metallized with either gold-germanium or gold-silicon and heated at 370.degree. C. in a forming gas to alloy the metallized layer to the wafer. A second, similar layer is then applied over the first alloyed layer. The wafer is then separated into individual chips or circuits, and the chips are eutectically bonded to the metallized substrate surface at 500.degree. C. in an ambient atmosphere. This process is not directed toward wafer scale integration applications.
To overcome the problems and limitations associated with the above described techniques, it is the object of this invention to provide a wafer to substrate bond wherein the resulting stresses in the wafer are lower than previously obtainable, while maintaining excellent mechanical support and high heat transfer capability within the bonded structure.
Another object of this invention is to provide a wafer to substrate bond without the use of significant amounts of gold or other precious metals.
Another object of this invention is to bond an entire wafer of three inch diameter or larger to a substrate material while providing for numerous points of low-ohmic electrical attachment at predetermined locations on the wafer for making electrical connections through the substrate for both power and signal leads.